# Lecture 31: SR Latch and Introduction to Clocked Flip-Flop Hello everybody.

We are now in week 7 of this particular course.

We shall begin Sequential Logic Circuit fromtoday’s class.

And we shall have a quick recap of week 6, I believe it was little bit heavy.

Because that was the last week of the combinatorialcircuit discussion, so lot of advanced things were there.

I hope you could assimilate them.

But as we have done in case of combinatorialcircuit – we made a soft start with introduction of basic gates and all.

Then we moved on to build more complex circuits.

So, similarly we shall start softly with basiccomponents of this sequential logic circuit by which we shall make more complex circuitin the a later classes, ok.

So, we discussed a magnitude comparison oftwo numbers, and how outputs like X greater than Y, X is equal to Y, X less than Y wasgenerated – were generated.

And in that case we had two kinds of approach:one is of course by subtraction and another is by comparing the more significant bitsof two numbers successively, ok.

And then we discussed arithmetic logic unit, and we saw that one device which is versatile in nature – depending on the selection unitit does perform one of the many different arithmetic or logic function.

And we saw that how all these devices canbe cascaded and more number of bits can be handled together.

Then we discussed unweighted codes, ok.

And then we saw that how gray code was advantageouswhere two consecutive numbers change by only 1-bit position.

And we also discussed the excess-3 code, wherewe saw that the BCD arithmetic, the way you had conducted before – that can be made simplerby excess-3.

And then we looked at error correction anderror detection codes, and in that context we defined Hamming distance.

And we saw that minimum Hamming distance ina particular coding paradigm; how that can be useful in deciding or in understandinghow many bits can be corrected or how many (error) bits can be detected, ok.

So, in that context we discussed a paritycode, standard parity code – even parity, odd parity code which we discussed in oneof the earlier weeks.

And also we discussed a new code – Hammingcode which can detect 2 error and correct 1 error, correct 1 error in bit position, ok.

So, this is was in brief what we discussedin the – and of course yes, we discussed multiplication and division, right.

And we saw bit you know, seemingly complexcircuit, but we had examples by which we could appreciate how the processing was done throughthe array based structures, in the unit cells, and finally the results were obtained, ok.

So, each of the cases we have defined theunit cell properly and looked at the solution by taking specific examples.

So, with this we start this week’s discussionas I said, we shall start with defining basic units of sequential logic circuit which ismemory element also called flip-flop.

But before that we shall see what is a bistablecircuit.

So, bistable circuit is something where thecircuit is stable in one of the two positions; bi stands for 2, right.

So, both the positions are stable, right.

So, if you look at this you know, a switchwhere you are applying a specific force by hand and all, and then you are connectingthe switch to this particular place.

Then you remove that hand pressure or youknow this whatever force, external force the switch will remain in that position.

But if you again put a force and bring ithere again it will remain there if you do not force it to go to another position.

So, each of these states is stable, ok.

So, in bistable circuit, we can store 1-bitof information.

That that is whether this output is high, Vcc or output is 0, right.

So, together you can store in the contextof binary representation of information, 1-bit information – we can store in the bistablecircuit.

Now moving over to digital circuits.

So, let us see if we have 2 inverters connectedone after another right, and we place a 0 volt here what will happen to it – to theinverter outputs in these cases.

The first will be this 0 volt to the 5 volt, right.

So, logic 0 will become logic over here andagain it gets inverted it is logic 0, ok.

This is understood.

Now while this ground is here you connecta feedback.

So, this feedback is key; this feedback isvery important in developing the basic cell and the sequential logic circuit, right.

In the combinatorial circuit we did not discuss, we did not include feedback.

So, the feedback comes in the sequential logiccircuit discussion.

So, you connect the feedback the way you haveseen from output to the input; why, there is no issue no ambiguity because this is 0volt and this is also 0 volt.

So, this is logic 0, this is also logic 0, this is logic 1.

Now if you remove this ground like this circuitbecomes like this.

What will happen to the circuit? It will remain at this 0 volt, this 0 volthere is driving this one, and this 0 volt is driving this 5 volt 5 volt this 0 volt.

So, it will remain in that place like youknow, as a stable formation right, this output will be 0 volt.

Now instead of this ground if you had startedwith a 5 volt here, then a feedback, ok.

And then you remove that you know, 5 volt;how would have been the output in this case? Output would have been stable 5 volt, ok.

So, this is what we can see a bistable circuitin the context of digital logic representation, right.

But what we find here that this way of youknow, applying external you know, this ground or 5 volt – this is a bit inconvenient.

So, you would look for something which ismore convenient to trigger from one particular state to another.

So towards that, let us look at this circuitwhere we are having instead of NOT gate we are having two NOR gates, ok.

So, you can see the feedback happening here.

And we can write, we can draw the same diagramin a different manner which is you know, cross-coupled, ok.

But there is one feedback you remember andone is in the forward path, but this is the way you can draw it, ok.

And we give these inputs some name S and Rand more about that will be clear very soon, ok.

And this is Q and we shall see that it happensto be the cases, where we are operating it the way we operate it, this V3 will be inverseof V2.

So, this is 0 volt, it will be 5 volt andvice versa.

So, that way we can write it to be Q bar, ok.

But we shall you know, see more of it in thesubsequent discussion, right.

So, consider that both of them are 0 0 ata given time, ok.

So, for a NOR gate 0 is a non-forcing inputok.

For OR and NOR, 1 is the forcing input.

For OR gate if 1 is there output will be 1irrespective of what is there in the other input.

And for NOR gate if 1 is there output willbe 0 irrespective of what is there in the other input.

Isn’t it? So, these are forcing inputs, right.

So, 0 0 is non-forcing input.

So, it will look at what are the other inputsby which the output will be decided.

So, then this 0 0 this is 1 right and this1, right is making it 0.

So, this 0 and 1 if the previous value was0, right then it will be 1.

And from the symmetry you can say if thiswas 1 this would, this would have been 0.

So, if you look at this truth table this iswhat you can see; that 0 0 then 0 0 and 1 1.

So, whatever had made the previous value 0or 1 that will be continued with when this two are 0.

So, the prior value of Q it is latched into, ok.

This prior value of Q is latched into, isit ok.

So, this is what we see with 0 0 present.

Now let us see if you present a 0 here anda 1 here, ok.

So, 1 is a forcing input irrespective of whatwere the past values or so, because this is coming from external.

So, this is – this will make it 0 right, andthis 0 0 we will make it 1 even if the previous value was 0 and 1, whatever.

So, ultimately this 1 forces it to be 0.

So, when this is 0 1 right, S is 0 and R is1, irrespective of what is the previous value the output is always 0, right.

And similarly again from symmetry this is1 and this is 0 this is the case, right.

This 1 will force it to be 0, this 0 0 thisis 1.

So, output will be 1, right Q will be 1.

So, this is what you can see, is it all right.

So if it was set, this now stands for – Sstands for set and R stands for reset.

So, when S is 1 and R is 0 we say this particularlatch this is basically – it is called latch because it is latching whenever we are puttinga 0 0 value.

So, whatever the past value which made theQ 0 or 1 because of 0 1 or 1 1, 1 0 that was present, it latches on to the past state;you know, the past value – past state.

So, that is why it is called latch.

So, this S stands for set and a R stands reset.

So, 1 0 is a setting of the latch and a 10 of S and R.

And 0 1 of S and R is resetting of the latch, ok.

Is it fine? Now what would happen if 1 1 was presentedhere? So, the output would have been 0 0 which isfine, I mean as such that is nothing, no ambiguity about it.

But after 1 1 if you try to put into thatresting state when the past value would be latched on to – so, after that if you put0 0 then what happens actually, that this 0 and this is external 0, so both are nownon-forcing, right.

And this 0 is over here.

Now depends I mean, which one of them getsthe 1 before the other.

Ideally one can say that both of them willget 1 you know, together.

So, that 1 will go to the feedback to therespective cases.

So, both 1 will become 0, ok.

So, that is the ideal case (but actually)where the propagation delays are identical – but whatever be the fabrication processor so we will see that one of them – which is not, for sure because of the way it getsfabricated, different transistors and other things are there in the circuit element, passiveelement so, one of them will be having a higher you know, propagation delay than the other.

So, that will respond slower which we cannotsay as a designer which one is you know, going to acquire the 1 value before the other, right.

So, that is something which becomes a bityou know unpredictable.

And a race between these two – who wins andthat is something which we would like to avoid in a SR latch use or application, ok.

So, that is why this 1 1, we are saying asnot allowed, clear.

So, how do we again look into you know, therepresentation part.

So, we will not write all those you know basicgates that we have used, instead we can prefer to put it in the form of a symbol which willhelp us in making bigger circuits, ok.

Otherwise this circuit will become a bit youknow clumsy – too many you know, logic gates and all.

So, when we say SR latch, so this is the waywe can put it.

And if you look at the textbook, two differentsymbols have been used.

In one case Q and Q bar are output – inside.

In both the cases, we will see SR is there, ok.

And that means, this is Q and this is theinvert of it that is what we have seen in the cases; the allowable cases, right.

And, in another representation Q bar – Q andQ bar taken – kept outside, but now there is an inverter, a bubble that is a NOT operation;that opposite operation that is being shown here.

So that means, whatever is the value hereit is opposite here, ok.

So, these are the two conventions we willfind in the textbook.

So, now we can, whatever truth table we hadseen before, now we can put it in a more compact form since we are trying to come up with acompact representation.

So, 0 0, so previous value is retained, previousstate is retained; 0 1 of S and R output is 0; 1 0 output is 1 – state becomes 1 and 11 is not allowed.

So, we had seen the way the NOR latch works.

So, have we – if we had connected you knowNAND gates in the same manner right, so what would have been the corresponding you know, truth table, ok.

So, in the NAND latch if you look at it.

So, NAND – for AND and NAND what is the forcinginput, 0 is the forcing input, ok.

So, if AND gate – 0 is there then irrespectiveof the other input, the output will always be 0.

And for NAND gate if 0 is there output willbe 1 irrespectively of the other input, .

So, in this case if you just look at thisfirst, this particular block, so we will see that if this we are giving it a name S barand R bar because that is the way we see – we shall see that relationship with this particulartable; the previous NOR latch.

So, if both of them are 0 0 right, so theoutput will be become 1 1, right.

And if both of them are 1 1, then it is non-enforcinginput.

So, it depends on the previous value.

So, if the previous value was say 0 and thiswas 1.

So, 0 and 1 this will be 1 and 1 1 it willbe 0.

So, previous value will be retained.

And previous value was 1 and 0.

So, this will go to 1 and 0 – 1 1 it willbecome this 0 it will go to 0 and this will become 1, and 1 will come over here and 11 it will become 0 ok; the other case, right.

You can see it from symmetry also, right.

So, this 1 1 is your previous state, right.

Similarly you can see 1 0 will be output willbe 0, 0 1 will be 1, and 0 0 is 1 1 because is forbidden because after that if 1 1 followsits output becomes unpredictable and depends on the race between this gate and this gate, ok.

Now if we are looking for a SR latch madeout of this and we want a truth table like this so what we need to do; we need to puta NOT gate before it, isn’t it.

So, a NOT gate before it and this NOT gateyou can get by a NAND gate also, by joining the 2 inputs, right.

So, this S bar becomes S here and R bar becomesR here.

So, you can use IC 7400 which has got youknow which is quad 2-input NAND gate to realise this one, fine.

So, this is one IC where within it, the SRlatch is already made, ok.

So, this particular IC if you see there are4 such latch one – IC 74279 – 2, 3, and 4.

So, 1 and 2 – is normal SR latch, ok.

Since it is made of NAND, so you can appreciatethat the input will be S 1 bar it is given a name S 1 and R bar, ok.

And in the other case you have got 2 inputs, S 1 bar and S 2 bar.

So, this is a 3 input NAND gate and this isR bar.

So, for the other gate we have got only oneinput.

And for that we shall have a truth table somethinglike this; how, ok.

So, you can see that if this particular caseall of them are 0 this is forbidden, because then the output will become 1, right.

And then if S 1 is 0 then this output is 1;this output is 1, right irrespective of S 2 is 0 or not because one of the forcing inputhas become 0 for NAND gate.

And at that time if R bar is 1.

So, this R bar is 1 right, just by consideringthe way we had considered it before we can see that this is 1 this R bar is 1, so 1 1it is 0 and 0 is fed back here – it is 1.

So, the output is 1.

Similarly, from symmetry, if S 2 was 0 atirrespective of S 1 the output will be 1.

And when both of them are 1, right; that means, this is non-enforcing and R bar is 0, then the output becomes 0, right.

And when all of them are 1 the output is inthe last state, ok.

So, this is what we can see for IC 74279, where the latch is already there inside the IC we do not need external connection usingNAND gates.

Now, one application of, there will be manyapplications, we shall see later and complex sequential logic circuit will be made.

So right now, we can see one application wherea debounce switch can be made using SR latch, ok.

So, what do we mean by debounce switch? So, when we are basically connecting a mechanicalswitch which is kind of you know having a spring load kind of thing.

So, whenever it is getting connected here, right.

So it will make a connection-disconnection, connection-disconnection, connection and then it will settle, so there will be a small vibration, right.

And when it disengages from here, this isthe output that we are talking about here when it disengages when it is connecting hereit is making a oscillation, but it is connected to 0, so it does not make any difference here.

So, only when it is getting connected at thisplace, getting closed, at that time there is a small vibration because of the you know, spring action that is there.

So, you will see you will see that wheneverit is getting closed for example here, so there is a small vibration taking place.

High-low, high-low it is getting disengagedgetting engaged, right.

When it is getting open and connecting tothis place, so it is a immediate so there is no such issue again it is getting here.

So, while ideal case we want this, but actuallythis is what is happening, clear.

So, this ringing can create issues, becauseit might say that number of you know 0s 1s you know, come into the picture which mightcreate difficulty.

So, it can trigger many events when, actuallyone event has taken place one such closure has taken place, it may count that 1 2 3 suchclosures have taken place.

And each closure might you know, can get countedand lead to certain action going forward, ok.

So, that is something which may be neededto be I mean, avoided in certain application.

So, for that we can use SR latch, right.

So, in the SR latch the switch is – one isS and another is R, right.

So, when it is disengaging from R and connectingto S, so there is a ringing over there, ok.

So, whenever that is happening, so 1 and 0the output is becoming one because it is getting set after that when it is getting, S becauseof the ringing, so it is becoming 0.

So, this is a 0.

So, previous state is retained, ok.

So, there is no issue with that, is it clear.

Similarly when it is coming to when it isgetting disengaged from S and coming to R right, it is getting disengaged no issue, but when it is connecting to R there is a small vibration.

So, R is becoming 1 0 1 0 for sometime.

So, whenever R becomes 1 for the first placeand this is 0 right, so it will get reset; so it has got reset.

After that during ringing this is – this remains0 and this is 0.

So, 0 0 means previous state is retained, ok.

So, if you now take output from here, therewill be no effect of bounce.

So, effectively we have got a debounce switch.

Now, we move little bit further, ok.

We look at further use of latch, the basiclatch by introducing an enable input, ok.

So, this is the basic SR latch which couldbe made up of NOR or NAND, as the case might be, ok.

So, that is – that part we shall see moreyou know, elaborate circuit later.

So, what we are doing here that we are putting, we are making SR go there through two AND gates like this, which has got an enable input.

So, when enable is 0 so these two outputsare 0.

So that means previous state is retained, ok.

So, this is the case – no change.

And when enable is 1, when enable is 1 andthat time depending on whatever we is this SR value this 1 1 is forbidden of course, the normal action takes place; is it clear.

So, we are not allowing the SR input to affectthe final output at any time – at all the time.

We are only allowing it when it is enabled, ok.

It is like strobe or you know, the kind ofthing that we had used before; for multiplexer, demultiplexer those circuits if you remember, ok.

So, the circuit, this circuit is acting onlywhen or made to work only when enable is at 1, ok.

So, what is its implication? So, if will look at a timing diagram, right.

So, you can see that when enable is at 0 likethis place, this place, this place, this place, right whatever changes are there it does notactually I mean, the Q will remain at that value in those cases.

So, t1 – t2 is the window in which any changecan be accommodated.

So, S was 1 and R was 0, and the Q was 0, so that makes I mean, if enable was not there whenever this S and R; S was 1 and R was 0- the Q would have been 1.

But the enable comes over here only here atthis point at t1.

So, at that time only Q will go to 1, right.

Now t1 to t2 there is no change in S and R.

So, Q remains at 1 at t2, at this point t2 after that enable is 0.

So, after that R becomes 1 and S becomes 0at some point of time over here.

But that effect does not get reflected inthe output Q – why? Because enable is at low, right.

So, again it gets trigger; again it gets theenable signal over here at t3.

At that time, it sees – it finds what is thevalue of S and R at that time.

So, S is 0 and R is 1.

So, that time it will go to – it will becomereset.

So, in between before the enable was thereif S and R had changed their value, it would not be captured by the final output, right.

So, only when the enable is there whateveris the value of S and R that gets transmitted and reflected in the final output.

So, this is the idea, ok.

So, whenever we want the SR flip-flop to workwe put the enable, otherwise we allow the S and R input to settle if there is any transientand all.

We do not want the final output gets you know, changed before S and R are you know, properly settled.

So, enable is giving that you know option- period for the inputs to get settled.

And this gives rise to what we end with today’sdiscussion – is called clocked SR flip-flop, ok.

So, the sequential circuit that we shall discussit is called – it will be actually synchronous sequential circuits.

So, most of the sequential circuit are synchronoussequential circuit, where the state change takes place synchronous with an external clock, ok.

So, this external clock actually totally decideshow the these different the sequential operation of the different kind of elements inside thecircuit, ok.

So, this particular clock would have you knowa waveform something like this right, so it goes high and low and all.

So, this is one clock cycle, right and ineach clock cycle you are looking for one state change if it is so desired by the input tothat particular bistable circuit.

In this case, this particular SR latch thatwe have discussed, ok.

And usually latch with a clock is called aflip-flop, ok.

But then you will see that in the text itis says latched SR flip-flop.

So, basically latch type is SR flip-flop.

So, basically they are referring to latchSR flip-flop, but in other text, generally speaking, presence of clock – flip-flop meansa presence of a clock, and latch means it is just the last stage of where the memorypart is there, where the value is latched into, ok.

So, that is the way distinction is often madein this particular field, .

So, then how this clocked SR flip-flop wouldlook like.

So, in place of now enable we are puttingthe clock, ok.

So, whenever the clock is high, right.

So, the input, change in the input can bethis S and R can be reflected in the output, ok.

So, in this case for SR flip-flop, this isa SR latch right, and this is the AND gate and this was enable as before.

So, we have put the clock over there, right.

And for NAND based circuit we remember thatthis was a NOT gate, right one 2-input NAND gate were put together to get S and R otherwisethis was S bar and R bar, right.

So, we can now use the other input of theNAND gate to put the clock, ok.

And we can see the clock is 0 this outputwill be 1 1, these are the forcing input for the NAND gate.

So, 1 1 means, right a for a NAND gate 1 1means previous state will be retained because that this is non-enforcing input for the NANDgate.

And only when it is 1, so this is now non-enforcing.

So, based on S and R the value will be transmittedhere and accordingly the final value will be arrived at, ok.

So, this is the basic SR clocked flip-flopcircuit.

And the symbol for this is this – the onethat you see here.

And this is also called level triggered flip-flop, because we’ll see edge triggered flip-flop in the next class.

So, level triggered flip flip-flop means wheneverclock is at a particular level.

So, that time it is allowed to trigger, allowedto change the state, ok.

And if we had put an inverter over here, aNOT gate over there, then the change would have been in this stages of the clock whenthe clock is low; isn’t it.

So, at that time would have said that, ifthis is positive level triggered high level triggered, so that would have been negativeor low level triggered, and at the time there would have been a bubble sign over here, ok.

That is a difference.

Is it clear?.

So, with this we conclude today’s class.

A bistable circuit has two stable states.

To summarize – its value changes only by externaltrigger.

SR latch – 0 0 is the input when the previousstate is latched into, 1 1 is not allowed.

And we can get bounce-free switch out of ordinaryswitches using SR latch.

And in gated SR latch or clocked SR latchthere is additional input which enables SR input to go – pass through, make changes inthe final output.

And in synchronous sequential circuit thisclock is very important and one state change we are looking in every clock cycle, synchronizedwith the clock, ok.

Thank you.

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