>> Good day.

This is Jim Pytel from ColumbiaGorge Community College.

This is Digital Electronics.

This lecture is entitledDesigning Synchronous Counters using D Flip Flops.

So we went over in ourprevious lecture how to design a synchronouscounter that could count in whatever sequence wewanted to use JK Flip Flops.

Okay, the little secretis I actually kind of showed you guysthe hard way first, and in comparison this DFlip Flop method is going to be substantially easier.

We're even going to usethe same two examples here to illustrate you canuse different technology to design a finitestate machine.

This first example was, again, our two-byte graycode up counter.

There's no external inputs, it's just more machine.

Its next state is dependentupon its present state only.

So we've got our present input, we can determine our next state.

And what I've drawn here on thebottom is D Flip Flops, okay? There's only one input, whereas, a JK Flip Flop has two inputs and four different modes, what's D Flip Flop do? Well, the value Q isbasically sampling D at those positive clockage[Assumed Spelling].

What we have to do is justmake D, the input D equivalent to what we want tothat next stage to be, and you can reallysimplify this is what is that next state input there? Well, that's D, we want our nextstate, our ideal next state.

Say, for example, right here, we're looking in this column, Q1, what do we wantthe input for D1 to be? Oh, we want it to bethis one right here, at that next positiveclockage we want it to be Q1, at the next positive edge, 4Q0, we want D0 to be that, so it's very simple.

All we're going to do is makeour K maps for D1 and D0, basically, Q1 is D1, that'sthe input for stage Q1.

What is the input for stage Q0? Well, it's D0, wewant those values.

What we're going to do is we'regoing to take D1, go ahead and populate our K maps, take D0 populate our K maps, and you should come up withsomething like this, okay? So we've populated the Kmaps for each stage's inputs, and now what I cando is just go ahead and take the minimumSOP expressions for each of the stage's inputs, determinethe minimum SOP expression for each stage inputs.

What I've resulted withis D1 is Q0, D0 is not Q1.

We'll go ahead and nextstep we're going to go ahead and implement the designand then what we're going to do we're goingto test it, okay? So look at our implementationthere, D0 is being fed, not Q1, and D1 is being fed Q0.

So let's go ahead and try atiming diagram analysis of this, and what we've gotis right here.

I've redrawn theimplemented circuit here.

So, first, let's go ahead andassume that we are in state 00, and again we are at2 byte gray code, let me just redraw the statediagram real quick just to make sure that we areimplementing exactly what we want to.

In a perfect world we are instate 00, we will transition to 01, then from there to 11, from there to 10, and back to 00.

So what I've drawn is theoutput stages, Q1 and Q0, but additionallyI've drawn not Q1, so we can do ourtiming diagram analysis.

First positive edge comesalong, what is the state of D0? Well, it's not Q1, which is currently a 1, at that positive edge Q0suddenly becomes 1 and, again, there's a slightdelay right there.

What is the input for stage Q1? Well, it's Q0, Q0 atthat positive edge if I remember right was a 0, sowhat does Q1 do, it stays a 0 and not Q1, obviously staying 1.

So what we did we went from 00up to 01, just like we expected in our timing diagram, so let's go ahead and see if we move to stage 11 now.

The next positive edge comesalong, sample Q0 is right there, samples not Q1 right there, D0'sinput is not Q1, so it's going to stay a 1, and now whatis the input for stage Q1? Well, it's D1, which is Q0, it's a 1 so what happens hereis Q1 is going to go up to 1.

We've made that transitionto, as we'd expect, 11.

What does not Q1 do? It goes back down to 0.

Go ahead and do the next input.

Obviously, we should hopethat we're going to go to 1, 0 and at that positive edge theD0 input is a 0, so that goes 2, 0 and then the D1 input atthat positive edge is a 1, so it's going to stay a 1.

We've made that transitionto 1, 0 as we'd expect for a gray code counter.

Next positive edge comes along, the D1 input is a 0, the D0 input is a 0.

Where have we gone? We've gone to 00 as we'd expect for our 2 byte graycode up counter.

So if you do these timingdiagrams over you see that entire sequence, 00, 01, 1, 0 – 1, 1 – all the way down to 1, 0 andwe're starting back again at 00.

So there's an alternativemethod to doing this and it's substantially easierthan using the JK Flip Flops.

So let's go ahead anduse what we've done here, using D Flip Flops.

I'll just do that sameexample that we did for design and synchronous countersusing JK Flip Flops.

So our next example of designingsynchronous counters using D Flip Flops is a finitestate machine that is actually a kneeling[Assumed Spelling] machine where its next stateis dependent not only on its present state, but some external input.

And if you're looking at the state machine diagramyou'll recognize this same one I did in the analysis ofsynchronous counters and the same one I did designingsynchronous counters using JK Flip Flops.

What I'm trying todo is show you that you could potentiallyimplement this same counter using a different technology, in this particular case a DFlip Flop and using D Flip Flops to design a synchronous counter like this is substantiallyeasier than JK Flip Flops because, again, there's only one input.

And what is the input Dfor each particular stage? What it should be, itshould be the next state.

So all we're going to do isjust take that next state and make that our D input.

What we did is we readour state machine diagram, determined our present stateand the external input, determine the next state, what is the D inputs.

Well, it is the next state.

What we could do is takethose D inputs and put those into individual canops[Assumed Spelling], so basically D1 isgoing into the D1 canop, D0 is going to the D0 canop.

Go ahead and evaluate thoseindividual expressions.

What I came up with for theD1 expression is X and Q1 and not Q0, or notX and Q0, or not X and not Q1, or not Q1 and Q0.

The D0 expression, we've gota big old group of four there, and it's not Q0, not X and not Q1, or X and Q.

So now whatI can do is go ahead and implement thisdesign and test it, and using a timingdiagram is going to be a little bitcomplicated for this.

We're actually goingto go ahead and kind of use a tabular analysis ofthis, to go ahead and see, okay, here are our D inputs, hereis the synchronous counter with the following D inputs.

And what I've done I've drawnour SOP expressions for D1 and D0, and notice here, too, D1 is matching this right here, D0 is matching this, so there's a little bit of a Flip Flop there, justgot to again stay organized.

And based on those input stateshere are our inputs right here, evaluate each one of thoseintermediate expressions for D1, based off those present inputsthere evaluate the intermediate stages for D0, based upon thoseintermediate stages evaluate D1 and D0.

What's the next state? Well, it is D1, D0.

So let's go ahead, at leastfor the D1 column, go ahead and evaluate thoseintermediate expressions for D1 and you should looksomething like this.

So the intermediate productterms for D1, let's go ahead and figure out what the or ofall those product terms are, it should look somethinglike this.

Now go ahead anddo this same thing for D0's intermediateexpressions, determine those values.

So based off those intermediateproduct terms evaluate D0, it should look something likethis, and there we have it.

What is the next stateQ1, Q0, the next time that positive edge comes on? Well, it's D inputs, D1and D0, so we can go ahead and just translate D1 and D0over to that next Q1, Q0 column.

It should look somethinglike this, and now go ahead and see does that present stateof 00 in mode 0, does it go – well, where does it go? It goes to 1, 1 – so anX is 0, it goes that way.

We are in present state 01mode 0, where do we go to, also to 1, 1 when X is 0.

What I'm doing is constructing, reconstructing this statediagram based on an analysis of what we came up with from thedesign and see does it, in fact, institute the state machinediagram which we're into, and you'll find as you gothrough these present states, next states for each mode because again this is modeX equals 0 and mode 1, it does in fact implement thedesired finite state machine.

Again, designingsynchronous counters, you can use JK FlipFlops or D Flip Flops, D Flip Flops are substantiallyeasier because, again, there's only one input there.

And we've designed a synchronouscounter using a JK Flip Flop, we've designed a synchronouscounter using D Flip Flops.

Let's go ahead and see howcounters work in VH DL.

Before we move onto thenext lecture, though, remember the two exercisesthat I gave you at the end of designing synchronouscounters using JK Flip Flops, the two binary/gray up counter and then the 3-byteeven-odd counter.

You might want to take a lookat those two suggested designs to go ahead and see if you canimplement those designs using D Flip Flops.

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